Referring now to FIG. 1, a prior art image sensor 100 comprises a regulated power supply 102, a sensing portion 104 and a control portion 106. The sensing portion 104 comprises a digital logic array 108 and an image sensor array 110. The image sensor array 110 comprises a pixel array 118 and first and second analog-to-digital converters 120, 122. The control portion 106 comprises a clock 112, an input-output (IO) port 114, which together forms a serial macro element 115 and a phase locked loop (PLL) 116.
Typically, a SMIA compatible image sensor requires a supply voltage of 1.2±0.2V to be compliant with the industry standard camera serial interface (CSI-2) specification. The voltage drop δV across the sensing portion 104 is determined by the relationship:δV=IRwhere R is the resistance of the digital element, and I is the current passing through the digital element.
The voltage drop across the sensing portion 104 is typically linear. The voltage drop may be sufficient to compromise the compatibility of the output of the image sensor 100 with the SMIA. That is, the voltage drop may be more that 100 mV.
Additionally, the connection of the power supply 102 remote from the control portion 106 via semiconductor substrate upon which the image sensor 100 is fabricated gives rise to high impedance between an external capacitor 124 and the control portion 106. A high impedance results in poor decoupling of current spikes between the power supply 102 and the control portion 106. Current spikes can cause cross-talk and jitter in the output signal.
A greater capacitance of the external capacitor 124 provides enhanced decoupling of current spikes. However, the provision of on-chip capacitance in excess of 100 nF, for example, is not practical due to the impedance of the semiconducting nature of the substrate upon which the image sensor 100 is fabricated.